A thin-film transistor (TFT) array is used in a liquid crystal panel or an organic electroluminescence (EL) panel, for example. Channel portions of thin-film transistors in the thin-film transistor array are made of amorphous silicon (a-Si) or polycrystalline silicon (poly-Si) which is a crystalline material. A crystalline silicon layer (poly-Si layer) of the channel portion of the thin-film transistor is typically provided by forming an amorphous silicon layer (a-Si layer) and then irradiating the amorphous silicon layer with laser light of an excimer laser or the like to instantly increase the temperature of the amorphous silicon layer so that the amorphous silicon layer is crystallized.
There are two types of thin-film transistor structures: one is a bottom-gate structure in which a gate metal is located on a substrate side with respect to x-Si (x is a or poly) of the channel portion; and the other is a top-gate structure in which a gate metal and a source-drain metal are located on a side opposite to the substrate side with respect to x-Si of the channel portion. The bottom-gate structure is mainly used in a-Si TFTs having a channel portion formed in an amorphous silicon layer, whereas the top-gate structure is mainly used in poly-Si TFTs having a channel portion formed in a crystalline silicon layer. Generally, the thin-film transistor structure used in a liquid crystal panel or an organic EL panel used in a large-area display device is the bottom-gate structure.
The bottom-gate structure may be used in a poly-Si TFT, which provides an advantage of lower manufacturing costs. Such a poly-Si TFT having the bottom-gate structure includes a crystalline silicon layer formed by irradiating an amorphous silicon layer with laser light to crystallize the amorphous silicon layer. In this method (laser annealing crystallization), the amorphous silicon layer is crystallized by heat generated by laser irradiation.
The thin-film transistors included in the thin-film transistor array used in, for example, an organic EL panel are particularly required to have uniform properties. To fulfill the requirements, techniques to form a crystalline silicon layer having uniform crystallinity over the surface of a substrate have been developed. However, the techniques have the following drawback (problem) when used for manufacturing thin-film transistors having a bottom-gate structure by laser annealing crystallization.
In manufacturing of thin-film transistors having a bottom-gate structure, an amorphous silicon layer is crystallized by laser annealing using laser light. The light absorbance of the amorphous silicon layer for the laser light is generally different between a region where a gate electrode is present (referred to as a “first region”) and a region where a gate electrode is not present (referred to as a “second region”). This is because the presence of a gate electrode causes a change in the effect of multiple interference of the laser light in a multi-layer thin film composed of an amorphous silicon layer and a gate insulating layer.
The difference in the light absorbance of the amorphous silicon layer between the two regions causes a difference in the increased temperature of the amorphous silicon layer between the two regions immediately after the laser irradiation. This results in uneven temperature distribution in the amorphous silicon layer. The crystallinity of the crystalline silicon layer formed by laser annealing crystallization highly depends on the increased temperature of the amorphous silicon layer as a result of laser irradiation. The uneven distribution of increased temperature in the amorphous silicon layer between the two regions causes a problem of unevenness in crystallinity of a resultant crystalline silicon layer.
For example, Japanese Unexamined Patent Application Publication No. 2007-220918 (Patent Reference 1) discloses a technique to solve the problem. Patent Reference 1 discloses that by using the technique, a gate insulating layer and an amorphous silicon layer are adjusted in thickness so that a thickness configuration can be achieved in which the amorphous silicon layer has uniform light absorbance across the first region and the second region. Unevenness in the increased temperature of the amorphous silicon layer between the regions immediately after laser irradiation is thus minimized so that a crystalline silicon thin film of uniform crystallinity can be formed over the surface of a substrate.
However, the technique disclosed in Patent Reference 1 has a problem that a crystalline silicon thin film of uniform crystallinity cannot be formed over the surface of a substrate in the case shown below. The problem is caused in the following way.
Generally, in a process of manufacturing a thin-film transistor array for a display device, an amorphous silicon layer and a gate insulating layer are formed using a process such as plasma-enhanced chemical vapor deposition (PECVD). A thin film formed using such a process has varied thicknesses to a certain degree within the surface of a substrate, depending on deposition conditions.
In this case, that is, in the case where the amorphous silicon layer or the gate insulating layer has varied thicknesses within the surface of a substrate, the light absorbance unavoidably varies according to the variation of the thicknesses (deviations from an targeted thickness).
The thickness of the amorphous silicon layer or the gate insulating layer still varies within the surface of the substrate even when the amorphous silicon layer and the gate insulating layer are formed to have thicknesses so that the light absorbance of the amorphous silicon layer is uniform across the first region and the second region. The amorphous silicon layer therefore fails to have uniform light absorbance across the first region and the second region throughout the surface of the substrate.
In other words, when an amorphous silicon layer or a gate insulating layer is formed using a process such as plasma-enhanced chemical vapor deposition, it is impossible to heat an amorphous silicon layer to a temperature uniform across the first region and the second region. This causes a problem of uneven crystallinity of a resulting crystalline silicon layer within the surface of the substrate.
There is a disclosed technique to address the problem in which the focus is on regions where channels of thin-film transistors are formed (first regions). In the technique, a crystalline silicon layer is formed so that the crystalline silicon layer has uniform crystallinity in the first regions (see Japanese Unexamined Patent Application Publication No. 2011-066243 (Patent Reference 2), for example).
According to Patent Reference 2, an amorphous silicon layer and a gate insulating layer are formed using conditions of thickness to minimize variation in light absorbance of the amorphous silicon layer above the first regions so that the crystallinity of the crystalline silicon layer above the first regions is uniform over the substrate. Use of such conditions allows for minimization of the impact of variation in the thickness of the amorphous silicon layer and variation in the thickness of the gate insulating layer on temperature increase of the amorphous silicon layer above the first regions as a result of laser annealing and on crystallinity of a resulting crystalline silicon layer.